Devices suffer from NBTI, HCI, and electromigration. In-field test using BIST or periodic scan testing can detect incipient failures, enabling predictive maintenance.
DFT modifies circuit design to simplify testing. Three cornerstone techniques are: Digital Systems Testing And Testable Design Solution
A fault model abstracts physical defects into logical malfunctions. The most common model is the (SSF), where a node is permanently stuck at logic 0 or 1. Despite its simplicity, SSF covers many real defects. Other models include: Devices suffer from NBTI, HCI, and electromigration
Scan testing works poorly for RAMs and ROMs. Memories have dense, regular structures perfect for algorithmic testing. Devices suffer from NBTI