Denoted by a "D" followed by a multiplier (e.g., D1 , D2 , D8 ). Higher numbers indicate larger transistors capable of driving higher capacitive loads.

| Code | Logic Function | | :--- | :--- | | | Inverter | | NAND2 | 2-input NAND | | NOR3 | 3-input NOR | | DFF | D-Flip-Flop (Data out on clock edge) | | DFFN | D-Flip-Flop with Negative edge trigger | | LAT | Latch | | AOI21 | And-Or-Invert (2 wide AND into OR, then Invert) | | OAI22 | Or-And-Invert | | BUF | Buffer | | MUX2 | 2-to-1 Multiplexer | | XOR2 | 2-input Exclusive OR | | SDFF | Scan D-Flip-Flop (includes scan input) | | SDFCN | Scan D-Flip-Flop with Clock Enable and Negated output |

So, BWP tells the placement tool: "This cell has built-in well ties."